Authors:
(1) Omer Rathore, Department of Physics, Durham University;
(2) Alastair Basden, Department of Physics, Durham University;
(3) Nicholas Chancellor, Department of Physics, Durham University and School of Computing, Newcastle University;
(4) Halim Kusumaatmaja, Department of Physics, Durham University and Institute for Multiscale Thermofluids, School of Engineering, The University of Edinburgh.
Table of Links
Methods
Results
Conclusions and Outlook, Acknowledgements, and References
Conclusions and Outlook
This study explored the utilization of quantum annealing as a strategic approach for the critical task of workload allocation to processors in parallel HPC applications. Initially focusing on less complex, gridbased applications, QA demonstrated improvements over simpler classical strategies, yet it did not conclusively surpass more sophisticated classical methods. A significant challenge for QA, unlike these classical methods, is the limited connectivity between physical qubits. This limitation results in a critical barrier to scalability, particularly given the fully connected nature of the problem at hand.
However, this drawback is somewhat mitigated in the context of the second application, which focused on load balancing in particle based codes. While the smallest problem configuration which was studied here is fully connected due to each cell’s proximity within the system, this is not expected to hold for larger problems. Recall that SPH kernels are characterized by compact support, this implies that larger problem graphs, while more extensive, are not likely to be fully connected. This subtlety enhances the feasibility of applying QA, especially in the Noisy Intermediate Scale Quantum (NISQ) era where interqubit connectivity can sometimes be a more critical constraint than the total number of qubits. Moreover, for simpler 2D/quasiplanar configurations this might not be as severe a constraint even for larger problem sizes. This is due to the compatibility between the problem graph and alignment of qubits with their couplers, which when implemented on a chip are inherently quasiplanar as well.
In addition, QA demonstrated an improvement in performance even against a state of the art classical method, despite the problem’s evolution into a complex multiobjective optimization. The Lagrange parameter formulation allows the user to explore the Pareto front and obtain highly optimised solutions tailored towards individual hardware architectures. Although this necessitated running a representative simulation and partitioning it repeatedly to explore the state space here, in general more cost effective methods such as machine learning could be used to estimate a good value a priori. This approach draws strong parallels with existing efforts that have endeavoured to do so for some of the other annealing parameters[79], [80]. The Ising formulation can also be readily extended to allow concurrent partitioning into multiple subsets simultaneously rather than recursively[24] to better accommodate larger problems.
Given the observed enhancements in solution quality and the reduced connectivity demands in larger problem graphs, it is conceivable that as annealers continue to evolve, they may become viable for graph partitioning tasks such as this. This is particularly relevant for hybrid applications such as load balancing where the majority of the algorithm could still be executed on CPUs, with only a select, complex segment offloaded to the quantum processor in tandem. As such, perhaps a heterogeneous architecture integrating both quantum and classical computing resources could be a strategic path forward. Particularly so in light of recent endeavours to strive towards such integrated systems[81], [82]. Moreover, one of the most time consuming components of the QA algorithm is currently the communication time between classical and quantum hardware and associated latency costs. This would be crucially reduced to almost negligible levels by colocating the respective chips in the same data center. The time for each anneal itself remains competitive at around 20µs compared to the roughly 15µs needed by METIS and is likely to improve with evolving hardware. However, this will be of comparatively little consequence as colocation will allow the system to run in parallel, thus best leveraging the inherent strengths of each respective system.
Acknowledgements
The authors would like to thank Dr Peter Draper at Durham University and Dr Matthieu Schaller at Leiden University for insightful discussions. Similarly, the authors are grateful to Prof Vivien Kendon at University of Strathclyde for useful comments and discussion on this work, as well as the rest of the QEVEC/QuANDiE teams. The authors acknowledge funding through UKRI EPSRC projects (EP/W00772X/2 and EP/Y004515/1). This work used the DiRAC@Durham facility managed by the Institute for Computational Cosmology on behalf of the STFC DiRAC HPC Facility (www.dirac.ac.uk). The equipment was funded by BEIS capital funding via STFC capital grants ST/K00042X/1, ST/P002293/1, ST/R002371/1 and ST/S002502/1, Durham University and STFC operations grant ST/R000832/1. DiRAC is part of the National eInfrastructure.
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